Design patterns have a wide variety of applications in the design, verification and test flows of integrated circuits (ICs). A design pattern comprises one or more polygons confined within a fixed 2-D space on one or more layers of a layout design; a polygon is formed by a set of edges; and an edge has two vertexes. Design patterns can be defined based on size and/or location specifications of these layout elements.
The simplicity of capturing complex geometric relationships with design patterns enables advanced physical verification and design methodology checks that were previously difficult or operationally impossible to create. The most common use of design patterns today is the visual identification of problematic topological configurations during manufacturing process simulations, failure analysis, and other verification/validation techniques. Simulations and layout analysis techniques can detect design features or configurations that will likely fail or negatively impact yield during manufacturing due to a variety of defects. Failure analysis can use post-manufacture silicon testing and yield analysis techniques to identify and isolate systematic defects that appear repetitively across dies and designs. These problematic configurations can be used to identify and isolate specific geometric configurations (patterns) directly from a layout design through pattern matching.
Before matching a pattern in a layout design, the pattern to be used in the search process (referred to as reference pattern) needs to be defined or captured. Pattern capture can be achieved directly using text descriptions. For some verification processes, complex geometries in a layout design are defined by selecting a desired configuration from a visual representation. Once recognized and defined, reference patterns can be added to a pattern library for use across multiple designs and dies, and many reference patterns can be carried forward from one node to the next with suitable adjustment.
A conventional reference pattern capture process often involved visual inspection and measurement by a designer familiar with the common failure mechanisms. The complexities of today's integrated circuits have made this task sufficiently complex that it can no-longer be reliably or confidently done by hand. The density of circuits and new technology requirements, like multi-patterning and FinFETs (3D gates), have resulted in the need for maintaining desired electrical performance characteristics during layout preparation and mask generation. Sensitive nets within the design may also require that they are “guarded” from other nets with aggressive switching and other electrical characteristics. During the lifetime operation of these circuits, performance degradation is often observed. While this degradation in isolation may be undesirable, uniform degradation of an entire functional block may be acceptable. In these cases, device orientation and symmetrical implementation often plays an important role to ensure symmetry in this degradation of the overall circuit. It is thus desirable to develop new pattern matching techniques that can identify electrically sensitive circuit elements in layout designs with minimum human effort and can process these identified elements to achieve the desired electrical characteristics.